1. Technical Field
The present invention relates to techniques for detecting and reducing defects formed on a wafer during submicron lithography.
2. Description of Related Art
Manufacturing processes for submicron integrated circuits require strict process control for minimizing defects on integrated circuits. Defects are the primary "killers" of devices formed during manufacturing, resulting in yield loss. Hence, defect densities are monitored on a wafer to determine whether a production yield is maintained at an acceptable level, or whether an increase in the defect density creates an unacceptable yield performance. Hence, the detection and monitoring of defects is critical to maintaining an acceptable yield.
Conventional approaches monitor defects by performing an electrical testing of completed products following the fabrication steps (i.e., semiconductor devices), and by monitoring for defects on product wafers using defect inspection tools at various steps of the testing process. However, defect detection is difficult for multilayer devices, since defects may be present within any one of at least five or six layers for the most simple integrated circuit. If a defect passes through more than one layer, a defect inspection tool may erroneously detect a defect on a given layer that was already present from a previous layer. As such, it may be difficult to identify which layer has a certain problem generating the defect. Hence, the monitoring of defects on a product wafer may overwhelm the ability to distinguish whether a defect on a certain layer is caused during the fabrication of a corresponding layer, or caused by an embedded defect formed from a previous layer.
Although certain yield management systems permit in-line monitoring to monitor process defects at certain processing stages, such in-line monitoring systems may still erroneously detect a defect on a given layer that was already present from a previous layer. Moreover, additional testing cannot be performed to identify and classify defects without removing the wafer from production, increasing the production delay and cost.
The testing costs may be even higher since the in-line monitoring techniques require the silicon wafer to be scrapped after analysis. Specifically, in-line defect analysis requires a clean wafer having a substantially low defect density of approximately 0-5 particles (0.2 microns or larger) per wafer. Hence, a silicon wafer used for in-line defect monitoring cannot be reused because the defect density of the used silicon wafer after any attempted cleaning is unacceptably high.
In addition, cleaning a monitored wafer for attempted reuse must not change its optical properties such as reflectivity, otherwise the testing machine may obtain a substantially different image of the wafer, resulting in a failure. Hence, the changes in the optical properties of the cleaned monitor wafer would cause additional delays due to recalibration of the in-line testing equipment to accommodate the changes in reflectivity.